Semiconductor Devices & Interconnect

p-n Junction

Built-in potential, depletion width, junction capacitance. Si: εr=11.7, n_i=1.0e10/cm³.

N_A (cm⁻³)

N_D (cm⁻³)

Applied bias V (V, − = reverse)

Temperature (K)

Square-law model. Cox=ε_ox/t_ox (ε_ox=3.9·ε₀). Auto-detects triode vs saturation.

µ (cm²/V·s)

t_ox (nm)

W/L

V_GS (V)

V_T (V)

V_DS (V)

R=ρL/(W·H); delay ≈ 0.69·R·C (Elmore). Use line capacitance per length.

ρ (µΩ·cm) — Cu≈2.2

Length L (µm)

Width W (nm)

Height H (nm)

Line capacitance (pF/cm)

MTTF ∝ J⁻ⁿ·exp(Ea/kT). Acceleration factor between stress & use conditions.

J_use (MA/cm²)

J_stress (MA/cm²)

T_use (°C)

T_stress (°C)

n (current exponent)

Ea (eV)

Waveguide + coupling + component losses → output power. SOI, ~1550 nm.

Propagation loss (dB/cm)

Waveguide length (cm)

Coupling loss / facet (dB)

# couplers (in+out)

Extra component loss (dB)

Input power (dBm)

Formula reference

p-n junction: V_bi=(kT/q)ln(N_A N_D/n_i²); depletion W=√[2ε(V_bi−V)/q·(1/N_A+1/N_D)]; capacitance C/A=ε/W. ε=εr·ε₀, ε₀=8.854e-14 F/cm.

MOSFET: Cox=ε_ox/t_ox. Saturation I_D=½µCox(W/L)(V_GS−V_T)²; triode I_D=µCox(W/L)[(V_GS−V_T)V_DS−V_DS²/2]. Saturation when V_DS ≥ V_GS−V_T.

Interconnect: R=ρL/(W·H); C=c′·L; Elmore delay t_d=0.69·R·C (∝ L²).

Electromigration (Black): MTTF=A·J⁻ⁿ·exp(Ea/kT); AF=(J_s/J_u)ⁿ·exp[(Ea/k)(1/T_u−1/T_s)], k=8.617e-5 eV/K.

Photonic link: total loss = α·L + N_c·coupling + components; P_out(dBm)=P_in−loss.